Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs

Yasuaki Ito, Koji Nakano


Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. The main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a Xilinx Virtex-6 FPGA with DSP blocks, each of which contains one multiplier and one adder. The experimental results show that, our coprocessor can verify 4.99×108 64-bit numbers per second. Also, we have implemented a multi-coprocessors system that has 380 coprocessors on the FPGA. The experimental results show that our multi-coprocessor system can verify 1.64×1011 64-bit numbers per second.


Hardware Algorithm; Collatz conjecture; FPGA Implementation; DSP blocks; Block RAMs

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